Samsung Electronics Accelerates Next-Gen Semiconductor Development by Applying Vertical Stacking to Logic Chips
Samsung Electronics is speeding up the development of next-generation semiconductors, bringing vertical stacking technology into the field of logic semiconductors (system semiconductors).
On June 17, Samsung Electronics announced that researchers at its semiconductor R&D center have developed the world’s first three-dimensional (3D) stacked transistor structure with a gate pitch of 42nm. The research paper recently won the Best Paper Award at the 2026 VLSI Symposium held in Kyoto, Japan.
This breakthrough carries far-reaching significance, as it extends the vertical stacking concept — originally created for memory semiconductors — to logic chip design. For NAND flash storage, Samsung broke capacity bottlenecks with V-NAND technology; in the DRAM segment, its HBM products dominate the core memory market powering the artificial intelligence (AI) era.
Kwon Wook-hyun from Samsung Electronics Semiconductor R&D Center stated: “Looking back on the research journeys of many senior engineers, we have broken through area limitations using vertical stacking architectures. V-NAND for NAND flash and HBM for DRAM are prime examples, and this evolutionary path naturally extends to logic semiconductors.”
Conventional logic semiconductors boost integration density by arranging transistors side-by-side on a flat plane. However, as device pitches shrink, electromagnetic interference becomes unavoidable, slowing further miniaturization. For this reason, the global semiconductor industry is racing to develop next-gen architectures that stack semiconductor devices vertically to lift overall performance.
Jung Young-chae, Chief Technology Officer of Samsung Electronics Semiconductor R&D Center, explained: “As transistor spacing shrinks, insulating layers grow thinner. Once the insulation thickness drops below a critical threshold, insulating performance fails entirely.” He added, “Vertically stacked devices eliminate horizontal scaling limits. The analogy is comparable to an area originally filled with single-family homes evolving into high-rise mixed-use buildings.”
With this new technology, Samsung’s research team achieved a 42nm gate pitch (transistor spacing), narrower than the industry’s current minimum of 48nm. The team also deployed an innovative architecture that directly connects upper and lower transistors to further boost integration density.
Kwon Wook-hyun noted: “42nm represents the smallest transistor pitch realized across the industry to date, and we are the first to implement a structure enabling direct interconnection between vertically stacked transistors.”
Samsung researchers project that this technology will strengthen the company’s competitiveness in semiconductors built for AI and high-performance computing (HPC) applications in the long run.
Hwang Dong-hoon, Principal Researcher at Samsung Electronics Semiconductor R&D Center, commented: “Vertical stacking architectures allow far more transistors to fit within the same silicon footprint. This design perfectly addresses AI-era customer demands for smaller die sizes, lower power consumption, and higher processing performance.”